Digital Logic


Q181.

Consider the following circuit with initial state Q0 = Q1 = 0. The D flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0.
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Q182.

Which of the following input sequences for a cross-coupled R-S flip-flop realized with two NAND gates may lead to an oscillation?
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Q183.

The characteristic equation of an SR flip-flop is given by :
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